1. Field of the Invention
The present invention relates to a light emitting apparatus, and optical printhead that employs the light emitting apparatus, and an image forming apparatus.
2. Description of the Related Art
A conventional image forming apparatus including an electrophotographic printer performs electrophotographic processes. A photoconductive drum is uniformly charged. The charged surface of the photoconductive drum is selectively exposed to light in accordance with print data to form an electrostatic latent image on the photoconductive drum. The electrostatic latent image is then developed with toner into a toner image. Subsequently, the toner image is transferred onto print paper, and is then fixed. This type of image forming apparatus employs a light source formed of light emitting diodes (LEDs) or light emitting thyristors.
LEDs emit light when current flows from anode to cathode. An LED turns on to emit light when current flows through its anode-to-cathode junction, and turns off not to emit light when current does not flow through the anode-to-cathode junction. When voltage is applied across the anode-to-cathode junction of an thyristor, the thyristor turns on to emit light if voltage is applied to the gate of the thyristor, and turns off not to emit light if voltage is not applied to the gate. Japanese patent preliminary publication No. 2007-81081 discloses one such image forming apparatus that employs a thyristor type optical printhead.
FIG. 13 is the circuit diagram of a conventional optical printhead. Referring to FIG. 13, an optical printhead 19 employs a shift register 30 formed of flip-flops 31-38 and buffers 41-48. Light emitting thyristors T1-T8 each include an anode, a cathode, and a gate.
The optical printhead 19 includes three input terminals: a shift data terminal SI, a shift clock terminal SCK, and a data terminal DATA. The data terminal DATA is connected to the anode of the thyristors. An anode current is supplied into a thyristor through the data terminal DATA, and drives the thyristor. The shift data terminal SI is connected to the D input terminal of the first flip-flop, i.e., flip-flop 31. The Q output terminal of each of the flip-flops 31-38 is connected to the D input terminal of the next flip-flop and to the input terminal of a corresponding buffer.
The output terminal of the buffer 41 serves as an output Q1 of the shift register 30, and is connected to the gate terminal of the thyristor T1. Likewise, the outputs Q2-Q8 of the shift register 30 are connected to the gates of the thyristors T2-T8. The shift clock terminal SCK of the shift register 30 is connected to the clock terminals of the flip-flops 31-38. The data terminal DATA of the optical printhead 19 is connected to the anodes of the thyristors T2-T8. The cathodes of the thyristors T2-T8 are connected to the ground.
FIG. 14 is a schematic diagram of a driver circuit illustrating a plurality of thyristors shown in FIG. 13. FIG. 14A illustrates the flip-flop 31, the buffer 41, and the thyristor T1 of the circuit shown in FIG. 13. An anode current Ia, a cathode current Ik, and a gate current Ig flow in directions shown by arrows, respectively. FIG. 14B illustrates the details of the circuit shown in FIG. 14A, showing the internal configuration of the buffer 41 and the thyristor T1.
Referring to FIG. 14B, the buffer 41 includes a first inverter formed of a PMOS transistor 51 and an NMOS transistor 52, and a second inverter formed of a PMOS transistor 53 and an NMOS transistor 54. Thyristors are devices of PNPN configuration in which a P-type semiconductor layer and an N-type semiconductor layer are stacked alternately one over the other to form a PNPN structure. The equivalent circuit of a thyristor may be expressed by the combination of a PNP 61 transistor and an NPN transistor 62. The emitter of the PNP transistor 61 corresponds to the anode of the thyristor T1, and the base of the PNP transistor 61 corresponds to the gate of the thyristor T1. The gate is also connected to the collector of the NPN transistor 62. The collector of the PNP transistor 61 is connected to the base of the NPN transistor 62. The emitter of the NPN transistor 62 corresponds to the cathode of the thyristor T1, and is grounded.
When the thyristor T1 conducts to emit light, the Q output of the flip-flop 31 is low. At this moment, the PMOS transistor 51 of the buffer 41 is ON, and the NMOS transistor 52 is OFF, so that the first inverter output becomes high. At this moment, the PMOS transistor 53 is OFF, and the NMOS transistor 54 is ON, and the output of the second inverter becomes low.
When the potential of the data terminal DATA increases, the thyristor T1 turns on. The gate current Ig flows in a path shown by dotted line. The gate current Ig is equivalent to the base current of the PNP transistor 61. The gate current Ig causes the PNP transistor 61 to turn on, so that the collector current flows through the PNP transistor 61. This collector current flows into the base of the NPN transistor 62 to cause current Ik1 to flow. The current Ik1 flows into the base of the PNP transistor 61 to ensure that the PNP transistor 61 turns on.
When a predetermined amount of current flows from anode to cathode, the thyristor T1 conducts to emits light. When the thyristor T1 emits light, the NPN transistor 62 is ON, and the voltage across the collector-emitter junction is the collector-emitter saturation voltage Vce(sat). The collector-emitter saturation voltage Vce(sat) is determined by the physical shape of the element, and the collector and base currents flowing through the NPN transistor 62. The Vce(sat) is typically in the range of 0.2 to 0.8 V.
At this moment, the gate voltage of the thyristor T1 is low and a part of the anode current supplied from the DATA terminal flows as the gate current Ig through the buffer 41 to the ground. Assume that the output of the buffer 41 is virtually disconnected from the gate of the thyristor T1. The output voltage VOL of the buffer 41 is determined by the drive capability of the NMOS transistor 54 (i.e., “ON” resistance of the NMOS transistor 54) and the gate current Ig of the thyristor T1. If VOL is lower than Vce (sat), then a part of the anode current that flows through the gate to the NMOS transistor 54 increases, and the collector current Ik2 of the NPN transistor 62 and the collector current Ik1 of the PNPN transistor 61 decrease.
As described above, the typical value of the Vce (sat) of the NPN transistor 62 is in the range of 0.2-0.8 V. The typical value of the output of the inverter constituted by the NMOS transistor 53 and NMOS transistor 54 changes between a value substantially equal to VDD and a value close to the ground potential (0V). Consequently, the NMOS transistor 54 has a greater capability to drive a load than the NPN transistor 62. Therefore, a large portion of the driver current supplied into the anode of the thyristor T1 will not flow into the collector of the NPN transistor 62 but into the NMOS transistor 54 through the gate of the thyristor T1.
If the buffer for driving the gate of a thyristor has a higher drive capability than an NPN transistor in the thyristor, a part of the drive current supplied into the anode terminal will flow into the gate terminal, causing a decrease in the anode-to-cathode current. This decreases light output of the thyristor.
In addition to the drive capability of the buffer to drive the gate of thyristor, fluctuation of the power supply voltage VDD during a printing operation is another factor that leads to changes in light output of the thyristor. The change in light output of the thyristor prominently impairs the print quality.